Synopsys and TSMC advance angstrom-scale chip design with certified EDA flows on A16 and N2P processes

Synopsys, Inc. announced continued collaboration with TSMC to accelerate semiconductor design at the angstrom scale, enabling AI and 3D multi-die innovation through advanced EDA and IP solutions certified for TSMC’s leading-edge A16 and N2P processes.

Key developments include:
- Certified digital and analog design flows for TSMC A16 and N2P, powered by Synopsys.ai, supporting improved power, performance, and design migration efficiency
- Ongoing development of EDA flows for TSMC’s upcoming A14 process
- Expanded 3D integration capabilities using Synopsys 3DIC Compiler and TSMC’s CoWoS® technology, supporting 5.5x reticle size interposers
- Certified IC Validator signoff physical verification for A16 and N2P, including 3Dblox and ESD rule support
- Broad portfolio of silicon-proven IP for high-speed interfaces including PCIe 7.0, 1.6T Ethernet, HBM4, UCIe, USB4, DDR5, LPDDR6, and MIPI standards
- Enhanced support for next-generation AI and HPC workloads with advanced PHY IP and integrated multi-physics analysis

Synopsys emphasized its role in delivering mission-critical tools and IP for cutting-edge system-on-chip (SoC) designs, enabling reduced development risk, faster time to market, and higher performance across a range of applications.