Synopsys announced a major collaboration with Intel Foundry to advance angstrom-scale chip design using Intel's 18A and 18A-P process technologies.

Synopsys has developed production-ready digital and analog design flows and the broadest IP portfolio for these advanced nodes, including support for RibbonFET and PowerVia technologies. The partnership also includes optimized tools for Intel’s new EMIB-T advanced packaging, enabling high-density, multi-die chip design.

Synopsys is also contributing to Intel's upcoming 14A-E node through early co-optimization efforts and has expanded its involvement in Intel’s ecosystem by joining both the Intel Foundry Accelerator Design Services Alliance and the new Intel Foundry Chiplet Alliance. These efforts aim to accelerate AI and high-performance computing chip development and foster wider adoption of Intel’s foundry services.

Synopsys and TSMC advance angstrom-scale chip design with certified EDA flows on A16 and N2P processes

Synopsys, Inc. announced continued collaboration with TSMC to accelerate semiconductor design at the angstrom scale, enabling AI and 3D multi-die innovation through advanced EDA and IP solutions certified for TSMC’s leading-edge A16 and N2P processes.

Key developments include:
- Certified digital and analog design flows for TSMC A16 and N2P, powered by Synopsys.ai, supporting improved power, performance, and design migration efficiency
- Ongoing development of EDA flows for TSMC’s upcoming A14 process
- Expanded 3D integration capabilities using Synopsys 3DIC Compiler and TSMC’s CoWoS® technology, supporting 5.5x reticle size interposers
- Certified IC Validator signoff physical verification for A16 and N2P, including 3Dblox and ESD rule support
- Broad portfolio of silicon-proven IP for high-speed interfaces including PCIe 7.0, 1.6T Ethernet, HBM4, UCIe, USB4, DDR5, LPDDR6, and MIPI standards
- Enhanced support for next-generation AI and HPC workloads with advanced PHY IP and integrated multi-physics analysis

Synopsys emphasized its role in delivering mission-critical tools and IP for cutting-edge system-on-chip (SoC) designs, enabling reduced development risk, faster time to market, and higher performance across a range of applications.

Synopsys Shareholders Approve Equity and Purchase Plan Amendments at Annual Meeting
SUNNYVALE, Calif. – Synopsys, Inc. (Nasdaq: SNPS) announced the results of its 2025 Annual Meeting of Stockholders, held on April 10. Shareholders approved key amendments to the company’s long-term incentive and stock purchase plans and voted on six proposals in total, including the re-election of all nine directors.

Shareholders approved the amended 2006 Employee Equity Incentive Plan, which adds 1.6 million shares to the plan and incorporates updates to align with Synopsys’ non-GAAP financial practices and compensation recovery policies. References to Section 162(m) of the Internal Revenue Code, now obsolete, were also removed.

Additionally, shareholders approved an amendment to the Employee Stock Purchase Plan, increasing the share reserve by 2.2 million and modernizing the plan’s change of ownership definition. The amendment also allows future flexibility to adjust the current 15% discount offered in purchase offerings.

All nine nominated directors were re-elected with strong support. Synopsys also received advisory approval for its named executive officer compensation and ratified the appointment of KPMG LLP as the company’s independent registered public accounting firm for fiscal year 2025.

However, shareholders did not approve a stockholder proposal regarding the ratification of golden parachutes, with a majority voting against the measure.

Voting tallies showed over 138 million shares represented at the meeting, constituting a quorum of the outstanding shares eligible to vote.

Let me know if you'd like a press-ready version tailored for media distribution or investor relations channels.

Synopsys has announced a major acceleration in chip design by integrating its electronic design automation (EDA) tools with NVIDIA's Grace Blackwell platform, achieving projected speedups of up to 30x for semiconductor development.

At GTC 2025, Synopsys unveiled enhancements to its EDA suite by leveraging NVIDIA CUDA-X libraries and the GB200 Grace Blackwell Superchip. Key improvements include:

- Circuit simulation: Synopsys PrimeSim achieves up to a 30x performance boost on NVIDIA's Blackwell platform, reducing simulation times from days to hours.
- Computational lithography: Synopsys Proteus, optimized with NVIDIA's cuLitho library, delivers up to 20x faster processing for manufacturing simulations.
- TCAD simulation: The Synopsys Sentaurus TCAD tool is projected to speed up time-to-results by 10x using NVIDIA GPUs.
- Materials engineering: Synopsys QuantumATK, accelerated with CUDA-X libraries, sees up to 100x performance improvements for semiconductor research.

In addition to computational advancements, Synopsys is integrating NVIDIA NIM inference microservices into its AI-powered Synopsys.ai Copilot, doubling productivity for engineers using generative AI in chip design.

The company is also optimizing more than 15 Synopsys EDA solutions for NVIDIA’s Grace CPU architecture, expanding its AI and accelerated computing capabilities in 2025.

With these innovations, Synopsys continues to push the boundaries of semiconductor design, significantly reducing development time and enhancing AI-driven workflows.

synopsys and vector informatik announced a strategic collaboration to accelerate the development of software-defined vehicles (sdvs) by integrating synopsys' electronics digital twin technology with vector's software factory solutions. the partnership aims to enhance software validation, reduce development costs, and improve engineering productivity for automakers and tier 1 suppliers.

key aspects of the collaboration include:
- integration of vector's microsar embedded software and canoe with synopsys' silver and virtualizer to create ready-to-use virtual electronic control units (vecus).
- leveraging the open-source sil kit to enable vehicle-level digital twins for better validation and compliance verification.
- implementing "shift-left" methodologies to transition automotive software development from sequential to agile workflows, accelerating time-to-market.

tom de schutter, senior vice president at synopsys, highlighted that their virtual prototyping technologies are already used by over 50 oems and tier 1 suppliers, underscoring the impact of this collaboration.

marcus eggenberger, vice president at vector informatik, emphasized that integrating synopsys' virtualization solutions with vector’s software factory will allow automotive organizations to scale up verification, validation, and software deployment efficiently.

the joint solution is designed to support software-defined vehicle architectures, from early development stages to over-the-air updates and dynamic data collection, ultimately enabling cost-effective and high-quality software engineering in the automotive industry.

more details are available at [vector](https://www.vector.com/sdv) and [synopsys](https://www.synopsys.com/automotive.html).

synopsys announced the launch of virtualizer native execution on arm-based hardware, aimed at accelerating software-defined product development for automotive, high-performance computing (hpc), and internet of things (iot) applications. this innovation enhances virtual prototype execution, allowing developers to optimize software workflows and reduce time to market.

the key benefits include:
- faster validation and simulation execution speeds using arm application processor cores.
- early software development integration with synopsys' extensive model libraries.
- hybrid prototyping support with synopsys zebu systems for software-based power estimation and architecture performance analysis.
- full system-level validation using digital twins for improved product testing.
- flexible deployment options on cloud or on-premise arm-based infrastructure such as aws, google, microsoft, nvidia, and ampere.

suraj gajendra, vice president of automotive product and software solutions at arm, emphasized that this tool enables developers to leverage arm-based cloud and edge computing, accelerating software development and reducing costs.

the virtualizer native execution suite is now available. more details can be found at [synopsys](https://www.synopsys.com/virtualizer).

Synopsys, Inc. Announces $10 Billion Senior Notes Offering to Fund ANSYS Acquisition
Sunnyvale, CA (March 5, 2025) – Synopsys, Inc. (NASDAQ: SNPS) has announced a $10 billion Senior Notes offering to finance the pending acquisition of ANSYS, Inc. and to refinance ANSYS’s outstanding debt.

Details of the Senior Notes Offering
On March 3, 2025, Synopsys entered into an Underwriting Agreement with BofA Securities, HSBC Securities, and J.P. Morgan Securities as representatives of the underwriters. The offering includes:

$1 billion of 4.550% Senior Notes due 2027
$1 billion of 4.650% Senior Notes due 2028
$2 billion of 4.850% Senior Notes due 2030
$1.5 billion of 5.000% Senior Notes due 2032
$2.4 billion of 5.150% Senior Notes due 2035
$2.1 billion of 5.700% Senior Notes due 2055
The Notes are issued under SEC Registration Statement No. 333-285378, with a Final Prospectus Supplement dated March 3, 2025.

Use of Proceeds
Synopsys intends to use the net proceeds from the offering, along with:

Cash on hand
Borrowings under its existing term loan credit agreement
A bridge commitment facility, if applicable
The funds will be used to:

Pay part of the cash portion of the merger consideration for ANSYS
Cover transaction fees and expenses
Repay ANSYS’s outstanding indebtedness
Invest temporarily in marketable securities until the merger closes
If the merger is not completed, a Special Mandatory Redemption (SMR) will be triggered for the 2027, 2028, 2030, and 2032 Notes, and the proceeds will be used for general corporate purposes, including debt repayment.

Closing Conditions
The Senior Notes offering is expected to close on March 17, 2025, subject to customary closing conditions.

Underwriters' Role
The underwriters and their affiliates have previously provided:

Credit facilities and financing arrangements to Synopsys
Arranged term loan and revolving credit agreements on February 13, 2024
Committed bridge financing on January 15, 2024
Additional Information
A copy of the Underwriting Agreement is filed as Exhibit 1.1 to Synopsys’s Form 8-K. This announcement is for informational purposes only and does not constitute an offer to sell or a solicitation to buy any securities.

Synopsys announced that the U.K. Competition and Markets Authority (CMA) has approved its proposed acquisition of Ansys in Phase 1, subject to previously announced divestitures. The company is working to secure regulatory approval in other jurisdictions and expects the transaction to close in the first half of 2025.

Synopsys CEO Sassine Ghazi emphasized that the acquisition will enable AI-powered design solutions that integrate electronics and physics, helping R&D teams drive innovation. The company remains focused on regulatory compliance and ensuring a smooth integration of Ansys' operations.

Synopsys, a leader in electronic design automation and semiconductor solutions, partners with various industries to enhance R&D capabilities. The acquisition of Ansys is expected to strengthen its position in AI-driven engineering and design.

Synopsys, Inc. has announced its financial results for the first quarter of fiscal year 2025, reporting revenue of $1.455 billion. While this represents a decline from $1.511 billion in the same quarter of the previous year, the company exceeded the midpoint of its revenue guidance.

GAAP earnings per diluted share for the quarter were $1.89, while non-GAAP earnings per diluted share stood at $3.03, surpassing guidance expectations. Synopsys has reaffirmed its full-year 2025 guidance, indicating confidence in its financial outlook.